| Name | Version | Summary | date |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| zhixin |
6.1.16a3 |
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded software development with ZhiXin's collaborative ecosystem, embracing declarative principles, test-driven methodologies, and modern toolchains for unrivaled success. |
2024-05-17 03:01:58 |
| tsfpga |
12.3.3 |
A flexible and scalable development platform for modern FPGA projects |
2024-05-14 07:47:37 |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| hdl-registers |
5.2.0 |
An open-source HDL register interface code generator fast enough to run in real time |
2024-05-07 11:54:42 |
| chisel4ml |
0.3.2 |
A Chisel based hardware generation library for highly quantized neural networks. |
2024-04-25 10:41:39 |
| platformio |
6.1.15 |
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded software development with PlatformIO's collaborative ecosystem, embracing declarative principles, test-driven methodologies, and modern toolchains for unrivaled success. |
2024-04-25 08:52:24 |
| myRIO-library |
1.3.3 |
A library to control the myRIO board from National Instruments |
2024-04-15 08:36:37 |
| pyrp3 |
2.0.1 |
Python utilities for RedPitaya |
2024-04-05 12:52:02 |
| super-ide |
1.4.8 |
A professional Cross-platform IDE. Cross-platform IDE and Unified Debugger. Static Code Analyzer and Remote Unit Testing. Multi-platform and Multi-architecture Build System. Firmware File Explorer and Memory Inspection. IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbedOS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V, STMicroelectronics (STM8/STM32), Teensy |
2024-04-05 05:04:27 |
| peakrdl-regblock |
0.22.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-04-01 05:27:07 |
| openflex |
0.1.4 |
Framework for Logic Synthesis and EXploration |
2024-03-24 05:02:05 |
| scisdk |
1.1 |
SDK for SciCompiler generated firmware |
2024-03-21 10:23:27 |